1. Field of the Invention
The invention generally relates to solid-state imaging devices, production methods thereof, and electronic devices provided with the solid-state imaging devices.
2. Description of the Related Art
Solid-state imaging devices are broadly classified into amplification type solid-state imaging devices, which are typically illustrated by CMOS (complementary metal-oxide semiconductor) image sensors, and charge transfer type imaging devices, which are typified by CCD (charge-coupled device) image sensors. The solid-state imaging devices have been used extensively in digital still cameras, digital camcorders, etc. In addition, as solid-state imaging devices mounted in mobile devices such as cellular phones with camera, PDA (personal digital assistant), etc., CMOS image sensors are used more frequently in recent years owing to relatively low source voltages and low power consumption characteristics among others.
In the CMOS solid-state imaging device including a pixel section and a peripheral circuit section, the configuration of isolation regions is known, which are formed with the same STI (shallow trench isolation) structure in both the pixel section and the peripheral circuit section. In addition, in the CMOS solid-state imaging device, another configuration of isolation regions in the pixel section is also known, which are formed with diffusion layers (see Japanese Unexamined Patent Application Publication No. 2005-347325 and Japanese Unexamined Patent Application Publication No. 2006-24786.). FIG. 1 is a schematic view illustrating an exemplary CMOS solid-state imaging device provided with isolation regions formed with diffusion layers.
Referring to FIG. 1, a CMOS solid-state imaging device 101 is provided, including a pixel section 103 having plural pixels arranged on a semiconductor substrate 102, and a peripheral circuit section 104 including logic circuits, formed on the periphery of the pixel section 103. In the pixel section 103, plural unit pixels 110 are disposed to be arrayed two-dimensionally, in which each of the unit pixels is formed, including a photodiode (PD) 107 serving as a photoelectric conversion element and several pixel transistors 108. These pixel transistors are representatively illustrated in FIG. 1 by the single pixel transistor 108 for the purposes of clarity, and the pixel transistor 108 is formed, including source/drain regions 109, and a gate insulating film and a gate electrode (not shown). A multilevel wiring layer 114 is formed above the pixel 110, including multiple wiring layers 113 having insulator films 112 formed thereunder for passivation, and an on-chip color filter 115 and an on-chip micro-lens 116 are formed on thus formed structure. Although not shown in the drawing, another multilevel wiring layer is similarly formed in the peripheral circuit section 104, including multiple layers of wiring having insulator films formed thereunder.
The isolation region 121 in the pixel section 103 is formed, including a p+ diffusion region 122 formed by ion implantations in the semiconductor substrate 102, and an insulator layer 123 of a silicon oxide film formed on the diffusion region. Although the insulator layer 123 is partially buried into the substrate 102, the buried depth h1 is set to be 50 nm or less, and the total thickness is set in the range approximately from 50 to 150 nm. In the peripheral circuit section 104, on the other hand, an isolation region 125 is formed with the STI structure, consisting of a trench 126 disposed in the semiconductor substrate 102, and an insulator layer 127 of a silicon oxide film buried into the trench 126. The buried depth h2 of the insulating layer 127 into the substrate 102 is in the range approximately from 200 to 300 nm, and its protrusion height h3 protruded out of the substrate surface is sufficiently lower than the protrusion height h4 of the insulator layer 123 in the pixel section 103.
In addition, an example of an isolation region formed in a pixel section is disclosed in Japanese Unexamined Patent Application Publication No. 2005-191262, and another example of isolation region in DRAM is disclosed in Japanese Unexamined Patent Application Publication No. 2007-288137.